Embedded systems are known, in which there are multiple master devices, such as processors of various kinds, and multiple resource devices, such as different types of memory, all interconnected by a bus matrix, or bus fabric, made up of different component buses. In order for the embedded system to operate, data must be transferred between these devices, typically in data bursts that contain multiple data words. A common occurrence in such systems is that there will be multiple simultaneous requests for the use of a resource such as a memory device or a resource such as a component bus of the bus fabric.
In such cases, one transaction must be given a higher priority than the other transaction or other transactions, and this can result in the overall performance of the system being compromised.
U.S. Pat. No. 5,668,975 describes one approach to arbitration, in the specific case of multiple requests for data from a memory block. In the method described in this document, each requested data transfer is split into a critical word plus one or more non-critical word. Then, each of the critical words is given a higher priority than each of the non-critical words, and the critical words and the non-critical words are handled in their respective priority orders.
However, this document does not provide any solution to the additional problems that arise in embedded systems a described above, in which arbitration between requests may be required at multiple points.